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wb2axip - A pipelined wishbone to AXI converter

  •    Verilog

Since the initial build of the core, I've added the WB to AXI lite bridge. This is also a pipelined bridge, and like the original one it is also formally verified. Since the project began, a full-fledged AXI4 to Wishbone bridge has been added to the project. This converter handles synchronizing the write channels, turning AXI read/write requests into pipeline wishbone requests, maintaining the AXI ID fields, etc. It ignores the AXI xSIZE, xLOCK, xCACHE, xPROT, and xQOS fields. It supports xBURST types of FIXED (2'b00) and INCR (2'b01), but not WRAP (2'b10) or reserved (2'b11). It does not (yet) support bridging between busses of different widths, so both the AXI and the WB bus must have the same width.