Displaying 1 to 18 from 18 results

keyboard-ip - PS/2 Keyboard IP written in VHDL for Xilinx FPGA

  •    VHDL

This PS/2 Keyboard IP is to be used with Xilinx FPGA, as it uses FIFO generated from ISE cores. It is written in VHDL.

s6_pcie_microblaze - PCI Express DIY hacking toolkit for Xilinx SP605

  •    C

This repository contains a set of tools and proof of concepts related to PCI-E bus and DMA attacks. It includes HDL design which implements software controllable PCI-E gen 1.1 endpoint device for Xilinx SP605 Evaluation Kit with Spartan-6 FPGA. In comparison with popular USB3380EVB this design allows to operate with raw Transaction Level Packets (TLP) of PCI-E bus and perform full 64-bit memory read/write operations. It's early version of my first much or less complicated FPGA project, so the speed is quite slow (around 1-2 Mb/s), but in upcoming releases it will be significantly increased by connecting PCI-E endpoint to MicroBlaze soft processor with AXI DMA engine. However, even such low speed is more than enough for reliable implementation of various practical attacks over PCI-E bus: to demonstrate applied use cases of the design, there's a tool for pre-boot DMA attacks on UEFI based machines which allow executing arbitrary UEFI DXE drivers during platform init. Another example shows how to use pre-boot DMA attacks to inject Hyper-V VM exit handler backdoor into the virtualization-based security enabled Windows 10 Enterprise running on UEFI Secure Boot enabled platform. Provided Hyper-V backdoor PoC might be useful for reverse engineering and exploit development purposes, it provides an interface for inspecting of hypervisor state (VMCS, physical/virtual memory, registers, etc.) from guest partition and perform the guest to host VM escape attacks. s6_pcie_microblaze.xise − Xilinx ISE project file.

Xilinx-ISE-Makefile - An example of how to use the Xilinx ISE toolchain from the command line

  •    Makefile

Install this through Cygwin on Windows. The name of the project, used as a name for certain intermediate files, and as the default name for the top-level module and constraints file.




wb2axip - A pipelined wishbone to AXI converter

  •    Verilog

Since the initial build of the core, I've added the WB to AXI lite bridge. This is also a pipelined bridge, and like the original one it is also formally verified. Since the project began, a full-fledged AXI4 to Wishbone bridge has been added to the project. This converter handles synchronizing the write channels, turning AXI read/write requests into pipeline wishbone requests, maintaining the AXI ID fields, etc. It ignores the AXI xSIZE, xLOCK, xCACHE, xPROT, and xQOS fields. It supports xBURST types of FIXED (2'b00) and INCR (2'b01), but not WRAP (2'b10) or reserved (2'b11). It does not (yet) support bridging between busses of different widths, so both the AXI and the WB bus must have the same width.

f32c - A 32-bit RISC-V / MIPS ISA retargetable CPU core

  •    VHDL

f32c is a retargetable, scalar, pipelined, 32-bit processor core which can execute subsets of either RISC-V or MIPS instruction sets. It is implemented in parametrized VHDL which permits synthesis with different area / speed tradeoffs, and includes a branch predictor, exception handling control block, and optional direct-mapped caches. The RTL code also includes SoC modules such as a multi-port SDRAM and SRAM controllers, video framebuffers with composite (PAL), HDMI, DVI and VGA outputs with simple 2D acceleration for sprites and windows, floating point vector processor, SPI, UART, PCM audio, GPIO, PWM outputs and a timer, as well as glue logic tailored for numerous popular FPGA development boards from various manufacturers. In synthetic integer benchmarks the core yields 3.06 CoreMark/MHz and 1.63 DMIPS/MHz (1.81 DMIPS/MHz with function inlining) with code and data stored in on-chip block RAMs. When configured with 16 KB of instruction and 4 KB of data cache, and with code and data stored in external SDRAM, the core yields 2.78 CoreMark/MHz and 1.31 DMIPS/MHz.

PoC - IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

  •    VHDL

PoC - “Pile of Cores” provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs. All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and constants. Additionally, a set of simulation helper packages eases the writing of testbenches. Because PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a clear hierachy.

CHaiDNN - HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

  •    C++

CHaiDNN is a Xilinx Deep Neural Network library for acceleration of deep neural networks on Xilinx UltraScale MPSoCs. It is designed for maximum compute efficiency at 6-bit integer data type. It also supports 8-bit integer data type. The design goal of CHaiDNN is to achieve best accuracy with maximum performance. The inference on CHaiDNN works in fixed point domain for better performance. All the feature maps and trained parameters are converted from single precision to fixed point based on the precision parameters specified by the user. The precision parameters can vary a lot depending upon the network, datasets, or even across layers in the same network. Accuracy of a network depends on the precision parameters used to represent the feature maps and trained parameters. Well-crafted precision parameters are expected to give accuracy similar to accuracy obtained from a single precision model.


RapidWright - Build Customized FPGA Implementations for Vivado

  •    

The RapidWright repository has been retired, effective immediately. The future availability of part of the repository in source format is being reviewed. Subject to these issues being resolved, we hope to re-launch an updated RapidWright repository. We are disappointed by this development and apologize for any inconvenience that it may cause to the community.

SDAccel_Examples - SDAccel Examples

  •    C++

Collection of examples geared at teaching the user best practices in how to use different features of SDAccel and start on their own application. Collection of examples in processor offloading to FPGA based compute units.

prjxray - Documenting the Xilinx 7-series bit-stream format.

  •    Verilog

Documenting the Xilinx 7-series bit-stream format. This repository contains both tools and scripts which allow you to document the bit-stream format of Xilinx 7-series FPGAs.

prjxray-db - Project X-Ray Database: XC7 Series

  •    Shell

This repo contains the bitstream documentation database for Xilinx Series 7 devices. HTML version of the Xilinx Series 7 BitStream is available on https://symbiflow.github.io/prjxray-db.

symbiflow-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation

  •    Python

The aim is to include useful documentation (both human and machine readable) on the primitives and routing infrastructure for these architectures. We hope this enables growth in the open source FPGA tools space. The documentation can be generated using Sphinx.

petalinux-docker - Dockerfile with Petalinux 2018.1/.2/.3

  •    Dockerfile

docker build --build-arg PETA_VERSION=2018.1 --build-arg PETA_RUN_FILE=petalinux-v2018.1-final-installer.run -t petalinux:2018.1 .

JSON-for-VHDL - A JSON library implemented in VHDL.

  •    VHDL

JSON-for-VHDL is a library to parse and query JSON data structures in VHDL. The complete functionality is hosted in a single VHDL package, without special dependencies. The JSON-for-VHDL library can be used to parse and query JSON data structures, which are read from disk. The data structure is read via VHDL file I/O functions and procedures and parsed into a internal compressed representation. While the parsing is done, a lightwight index is created to ease the navigation on the data structure.