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dblclockfft - A configurable C++ generator of pipelined Verilog FFT cores

  •    C++

One sample in per clock, with the i_ce line being high for every incoming sample--up to one sample per clock. There's also options to run with at least one clock between samples, or even two clocks between samples (or more). This mode uses 3, 2, or 1 multiplies per FFT stage respectively. Eventually, I want to support a real FFT mode which will accept real samples input, and alternately produce real and imaginary samples output--or the converse for the inverse FFT.

sdspi - SD-Card controller, using a SPI interface that is (optionally) shared

  •    Verilog

This Verilog core exports an SD card controller interface from internal to an FPGA to the rest of the FPGA core, while taking care of the lower level details internal to the interface. Unlike the other OpenCores SD Card controller which offers a full SD interface, this controller focuses on the SPI interface of the SD Card. While this is a slower interface, the SPI interface is necessary to access the card when using a XuLA2 board, or in general any time the full 9--bit, bi--directional interface to the SD card has not been implemented. Further, for those who are die--hard Verilog authors, this core is written in Verilog as opposed to the XESS provided demonstration SD Card controller found on GitHub, which was written in VHDL. For those who are not such die--hard Verilog authors, this controller provides a lower level interface to the card than these other controllers. Whereas the XESS controller will automatically start up the card and interact with it, this controller requires external software to be used when interacting with the card. This makes this SDSPI controller both more versatile, in the face of potential changes to the card interface, but also less turn-key. While this core was written for the purpose of being used with the ZipCPU, as enhanced by the Wishbone DMA controller used by the ZipCPU, nothing in this core prevents it from being used with any other architecture that supports the 32-bit Wishbone interface of this core.