Displaying 1 to 9 from 9 results

80x86 - 80186 compatible SystemVerilog CPU core and FPGA reference design

  •    C++

The S80186 IP core is a compact, 80186 binary compatible core, implementing the full 80186 ISA suitable for integration into FPGA/ASIC designs. The core executes most instructions in far fewer cycles than the original Intel 8086, and in many cases, fewer cycles than the 80286. The core is supplied as synthesizable SystemVerilog, along with a C++ reference model, extensive tests, a reference BIOS implementation and reference FPGA designs. This will build the Docker containers and then perform a release build and run all of the tests.

ipxact2systemverilog - Translates IPXACT XML to synthesizable VHDL or SystemVerilog

  •    Python

This software takes an IP-XACT description of register banks, and generates synthesizable VHDL and SystemVerilog packages and ReStructuredText documents. It ONLY considers register bank descriptions. The software does not generate OVM or UVM testbench packages. In the example/tb directory there is an example of how to use the generated packages. You can use http://rst2pdf.ralsina.me to make a pdf from the generated reStructuredText. You can use http://pandoc.org/demos.html to convert to almost any fileformat.

fpga-virtual-console - VT220-compatible console on Cyclone IV EP4CE55F23I7

  •    SystemVerilog

This project implements a VT220-compatible console with extra color support on Cyclone IV EP4CE55F23I7. The experimental board has PS/2 keyboard input and HDMI video output, with UART transceiver to communicate with a computer. The project is developed under Quartus Prime Lite 18.0, we do not provide any warranty for successful compilation on any other software.

USB - FPGA USB 1.1 Implementation

  •    SystemVerilog

Altera Cyclone II FPGA Starter Development Kit. The USB D+ and D- pads were configured for Low Speed.

axi_node - AXI X-Bar

  •    SystemVerilog

This is an implementation of an AXI interconnect with configurable number of slave and master ports. The AXI interconnect supports multiple regions and allows runtime configuration of the memory map via AXI or APB. It was written for the use in the PULP platform.

slang - SystemVerilog compiler and language services

  •    C++

Parser and compiler library for SystemVerilog. Experiment with parsing, type checking, and error detection live on the web (this tool is inspired by Matt Godbolt's excellent Compiler Explorer). It's still pretty rough but useful for exploring the interactive behavior of the toolchain.