Displaying 1 to 4 from 4 results

dblclockfft - A configurable C++ generator of pipelined Verilog FFT cores

  •    C++

One sample in per clock, with the i_ce line being high for every incoming sample--up to one sample per clock. There's also options to run with at least one clock between samples, or even two clocks between samples (or more). This mode uses 3, 2, or 1 multiplies per FFT stage respectively. Eventually, I want to support a real FFT mode which will accept real samples input, and alternately produce real and imaginary samples output--or the converse for the inverse FFT.

dspfilters - A collection of demonstration digital filters

  •    Verilog

A description (and implementation of) the two simplest filters I know of.

vgasim - A Video display simulator

  •    Verilog

This repository contains a Video Controller. This controller includes not only the low-level framer, but also a bus controller to read values from memory to then be displayed on the screen. This is the basis of a frame buffer approach to video. This capability is fully demonstrated via the Verilator based simulator.

wb2axip - A pipelined wishbone to AXI converter

  •    Verilog

Since the initial build of the core, I've added the WB to AXI lite bridge. This is also a pipelined bridge, and like the original one it is also formally verified. Since the project began, a full-fledged AXI4 to Wishbone bridge has been added to the project. This converter handles synchronizing the write channels, turning AXI read/write requests into pipeline wishbone requests, maintaining the AXI ID fields, etc. It ignores the AXI xSIZE, xLOCK, xCACHE, xPROT, and xQOS fields. It supports xBURST types of FIXED (2'b00) and INCR (2'b01), but not WRAP (2'b10) or reserved (2'b11). It does not (yet) support bridging between busses of different widths, so both the AXI and the WB bus must have the same width.