riscv_vhdl - VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".

  •        46

This repository provides open source System-on-Chip implementation based on 64-bits CPU "Rocket-chip" distributed under BSD license. SOC source files either include general set of peripheries, FPGA CADs projects files, own implementation of the Windows/Linux debugger and several examples that help to run your firmware on almost any FPGA boards. Satellite Navigation (GPS/GLONASS/Galileo) modules were stubbed in this repository and can be requested on gnss-sensor.com. RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

http://sergeykhbr.github.io/riscv_vhdl/
https://github.com/sergeykhbr/riscv_vhdl

Tags
Implementation
License
Platform

   




Related Projects

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

  •    Assembly

For commercial support, please contact spinalhdl@gmail.com. The following numbers were obtained by synthesizing the CPU as toplevel without any specific synthesis options to save area or to get better maximal frequency (neutral). The clock constraint is set to an unattainable value, which tends to increase the design area. The dhrystone benchmark was compiled with the -O3 -fno-inline option. All the cached configurations have some cache trashing during the dhrystone benchmark except the VexRiscv full max perf one. This of course reduces the performance. It is possible to produce dhrystone binaries which fit inside a 4KB I$ and 4KB D$ (I already had this case once) but currently it isn't the case. The CPU configurations used below can be found in the src/scala/vexriscv/demo directory.

riscv-boom - Berkeley Out-of-Order Machine

  •    Scala

This is the source repository for the RV64G RISC-V superscalar Berkeley Out-of-Order Machine (BOOM), written in the Chisel hardware construction language. BOOM is a synthesizable core that targets ASIC processes. It can run on an FPGA (50 MHz on a zc706), but optimizing it to be an FPGA soft-core is a non-goal. For documentation on BOOM visit (https://ccelio.github.io/riscv-boom-doc).

ghdl - VHDL 2008/93/87 simulator

  •    VHDL

A new GitHub organization was created (2017-12-20) and the main repo was moved from github.com/tgingold/ghdl to github.com/ghdl/ghdl. Old refs will continue working, because permanent redirects are set up. However, we suggest every contributor to update the remote URLs in their local clones. See Changing a remote's URL. This directory contains the sources of GHDL, the open-source compiler and simulator for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyse and elaborate sources to generate machine code from your design. Native program execution is the only way for high speed simulation.

vunit - VUnit is a unit testing framework for VHDL/SystemVerilog

  •    VHDL

VUnit is an open source unit testing framework for VHDL/SystemVerilog released under the terms of Mozilla Public License, v. 2.0. It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn't replace but rather complements traditional testing methodologies by supporting a "test early and often" approach through automation. Contributing in the form of code, feedback, ideas or bug reports are welcome. Read our contribution guide to get started.

rocket-chip - Rocket Chip Generator

  •    Scala

This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core. For more information on Rocket Chip, please consult our technical report. To build the rocket-chip repository, you must point the RISCV environment variable to your riscv-tools installation directory.


aws-fpga - Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

  •    VHDL

The AWS EC2 FPGA Hardware and Software Development Kits include two portions: Development workflows for developing Amazon FPGA Image (AFI) with the HDK or the GUI workflow, and SDK for using AFIs on FPGA-enabled EC2 instances such as F1.The Release Notes document covers the list of supported features, programming environments, and known restrictions.

VHDL-based WiMAX design

  •    

WiMAX, an emerging technology that is bound to catch us as swiftly as WiFi did but not without sweat! .We aim to understand the intricacies of what makes a WiMAX system. By efficient use of VHDL amp; simulation software,IP cores will be verified in an FPGA.

riscv-isa-sim - Spike, a RISC-V ISA Simulator

  •    C

Spike, the RISC-V ISA Simulator, implements a functional model of one or more RISC-V processors. Spike is named after the golden spike used to celebrate the completion of the US transcontinental railway.

ariane - Ariane is a 6-stage RISC-V CPU

  •    SystemVerilog

Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M and C extensions as specified in Volume I: User-Level ISA V 2.1 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore it is compliant to the draft external debug spec 0.13. It has configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer and branch history table). The primary design goal was on reducing critical path length.

fusesoc - FuseSoC is a package manager and a set of build tools for FPGA/ASIC development

  •    Python

FuseSoC is an award-winning package manager and a set of build tools for HDL (Hardware Description Language) code. Its main purpose is to increase reuse of IP (Intellectual Property) cores and be an aid for creating, building and simulating SoC solutions.

FPGA C Compiler

  •    C

FpgaC compiles a subset of the C language to net lists which can be imported into an FPGA vendors tool chains. C provides an excellent alternative to VHDL/Verilog for algorithmic expression of FPGA reconfigurable computing tasks. More info in wiki.

sister

  •    C

Sister is high-level synthesizer for SoC design . It analyzes SystemC(based on C++ language) source code and creates Verilog HDL source code.

riscv-tools - RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)

  •    Shell

Note for OS X: We recommend using Homebrew to install the dependencies (libusb dtc gawk gnu-sed gmp mpfr libmpc isl wget automake md5sha1sum) or even to install the tools directly. This repo will build with Apple's command-line developer tools (clang) in addition to gcc.

Free tools and cores for FPGAs

  •    C

Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.

Open-Source-FPGA-Bitcoin-Miner - A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs

  •    VHDL

To promote the free and open development of an FPGA based Bitcoin mining solution.Project is fully functional and allows mining of Bitcoins both in a Pool and Solo. It also supports Namecoins.

FPGA-Based Oscilloscope

  •    C

Oscilloscope components, including 100MHz quad A/D, VHDL code for Xilinx FPGA, and driver for Octave or Matlab.

parallella-hw - Parallella board design files

  •    VHDL

This repository contains open source board and FPGA designs associated with the Parallella project. All Parallella related FPGA sources have been moved to the OH! library library and released under MIT license.

HDLObf

  •    Java

HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.

EveSoc

  •    Python

This project's goal is to provide a simple but extendable SOC (System On Chip) that can be loaded into an FPGA in order to quickly test custom coprocessors and evaluate their robustness against SCA (Side Channel Attacks) or others physical attacks.

VHDLC

  •    C++

VHDLC is a VHDL to C++ translator aiming at full VHDL '93 compliance. It provides the translator and supporting VHDL libraries for the target host C++ compiler.