f32c - A 32-bit RISC-V / MIPS ISA retargetable CPU core

  •        25

f32c is a retargetable, scalar, pipelined, 32-bit processor core which can execute subsets of either RISC-V or MIPS instruction sets. It is implemented in parametrized VHDL which permits synthesis with different area / speed tradeoffs, and includes a branch predictor, exception handling control block, and optional direct-mapped caches. The RTL code also includes SoC modules such as a multi-port SDRAM and SRAM controllers, video framebuffers with composite (PAL), HDMI, DVI and VGA outputs with simple 2D acceleration for sprites and windows, floating point vector processor, SPI, UART, PCM audio, GPIO, PWM outputs and a timer, as well as glue logic tailored for numerous popular FPGA development boards from various manufacturers. In synthetic integer benchmarks the core yields 3.06 CoreMark/MHz and 1.63 DMIPS/MHz (1.81 DMIPS/MHz with function inlining) with code and data stored in on-chip block RAMs. When configured with 16 KB of instruction and 4 KB of data cache, and with code and data stored in external SDRAM, the core yields 2.78 CoreMark/MHz and 1.31 DMIPS/MHz.




Related Projects

Open-Source-FPGA-Bitcoin-Miner - A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs

  •    VHDL

To promote the free and open development of an FPGA based Bitcoin mining solution.Project is fully functional and allows mining of Bitcoins both in a Pool and Solo. It also supports Namecoins.

riscv-boom - Berkeley Out-of-Order Machine

  •    Scala

This is the source repository for the RV64G RISC-V superscalar Berkeley Out-of-Order Machine (BOOM), written in the Chisel hardware construction language. BOOM is a synthesizable core that targets ASIC processes. It can run on an FPGA (50 MHz on a zc706), but optimizing it to be an FPGA soft-core is a non-goal. For documentation on BOOM visit (https://ccelio.github.io/riscv-boom-doc).

icestudio - :snowflake: Visual editor for open FPGA boards

  •    Javascript

Visual editor for open FPGA boards. Built on top of the Icestorm project using Apio. Check the Documentation for more information.

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

  •    Assembly

For commercial support, please contact spinalhdl@gmail.com. The following numbers were obtained by synthesizing the CPU as toplevel without any specific synthesis options to save area or to get better maximal frequency (neutral). The clock constraint is set to an unattainable value, which tends to increase the design area. The dhrystone benchmark was compiled with the -O3 -fno-inline option. All the cached configurations have some cache trashing during the dhrystone benchmark except the VexRiscv full max perf one. This of course reduces the performance. It is possible to produce dhrystone binaries which fit inside a 4KB I$ and 4KB D$ (I already had this case once) but currently it isn't the case. The CPU configurations used below can be found in the src/scala/vexriscv/demo directory.


  •    Java

RapidSmith is a research-based FPGA CAD tool framework written in Java for modern Xilinx FPGAs. Based on XDL, its objective is to serve as a rapid prototyping platform for research ideas and algorithms relating to low level FPGA CAD tools.

FPGA-Based Oscilloscope

  •    C

Oscilloscope components, including 100MHz quad A/D, VHDL code for Xilinx FPGA, and driver for Octave or Matlab.

hdl - HDL libraries and projects

  •    Verilog

Analog Devices Inc. HDL libraries and projects. This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.

ariane - Ariane is a 6-stage RISC-V CPU

  •    SystemVerilog

Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M and C extensions as specified in Volume I: User-Level ISA V 2.1 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore it is compliant to the draft external debug spec 0.13. It has configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer and branch history table). The primary design goal was on reducing critical path length.

Rapid HDL


Rapid Hardware Definition Language (Rapid HDL) is an object oriented C# software library in to script/generate/build synthesizable Verilog for FPGA hardware and software co-design in Visual Studio. It also integrates and automates Xilinx or Mentor Graphics build tools.

Groundhog - Serial ATA Host Bus Adapter


Groundhog implements a SATA host bus adapter. This Verilog-based project creates an easy-to-use interface between a user circuit on a Xilinx FPGA and a SATA hard drive or SSD.

LoonBoard Unified Bootloader - LUB

  •    C

A complete bootloader that can load both an AVR processor and a Xilinx FPGA using a DataFLASH device to store programs.

rocket-chip - Rocket Chip Generator

  •    Scala

This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core. For more information on Rocket Chip, please consult our technical report. To build the rocket-chip repository, you must point the RISCV environment variable to your riscv-tools installation directory.

lattice-release - Lattice

  •    Go

Lattice was a Cloud Foundry project focused on delivering the Diego application scheduler into the hands of users as quickly as possible before Diego was fully integrated to Cloud Foundry. Lattice served that purpose well, but now Diego is available as the application scheduler for Cloud Foundry, and Cloud Foundry is the best way to use Diego. Therefore, Lattice is no longer actively maintained. NOTE: Ubuntu 14.04 LTS does not install a compatible version of Vagrant by default. You can upgrade the version that you get out of the box by downloading the .deb file from Vagrant.

RSA-and-LLL-attacks - attacking RSA via lattice reductions (LLL)

  •    TeX

This repo host implementations and explanations of different RSA attacks using lattice reduction techniques (in particular LLL). First, we'll see how Coppersmith found out that you could use lattice reduction techniques to attack a relaxed model of RSA (we know parts of the message, or we know parts of one of the prime, ...). And how Howgrave-Graham reformulated his attack.

LatticeLSTM - Chinese NER using Lattice LSTM. Code for ACL 2018 paper.

  •    Python

Lattice LSTM for Chinese NER. Character based LSTM with Lattice embeddings as input. Models and results can be found at our ACL 2018 paper Chinese NER Using Lattice LSTM. It achieves 93.18% F1-value on MSRA dataset, which is the state-of-the-art result on Chinese NER task.

OpenLB - Library for Lattice Boltzmann Simulations

  •    C++

OpenLB is a C++ library for the implementation of lattice Boltzmann simulations which addresses a vast range of problems in computational fluid dynamics. The package is mainly intended as a programming support for researchers and engineers who simulate fluid flows by means of a lattice Boltzmann method.

lattice - Lattice methods in TensorFlow

  •    Python

This is an implementation of Monotonic Calibrated Interpolated Look-Up Tables in TensorFlow. These are fast-to-evaluate and interpretable lattice models, also known as interpolated look-up tables. This library also provides a rich and intuitive set of regularizations and monotonicity constraints configurable per feature.

aws-fpga - Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

  •    VHDL

The AWS EC2 FPGA Hardware and Software Development Kits include two portions: Development workflows for developing Amazon FPGA Image (AFI) with the HDK or the GUI workflow, and SDK for using AFIs on FPGA-enabled EC2 instances such as F1.The Release Notes document covers the list of supported features, programming environments, and known restrictions.

freedom - Source files for SiFive's Freedom platforms

  •    Scala

This repository contains the RTL created by SiFive for its Freedom E300 and U500 platforms. The Freedom E310 Arty FPGA Dev Kit implements the Freedom E300 Platform and is designed to be mapped onto an Arty FPGA Evaluation Kit. The Freedom U500 VC707 FPGA Dev Kit implements the Freedom U500 Platform and is designed to be mapped onto a VC707 FPGA Evaluation Kit. Both systems boot autonomously and can be controlled via an external debugger. Please read the section corresponding to the kit you are interested in for instructions on how to use this repo.