usbcorev - A full-speed device-side USB peripheral core written in Verilog.

  •        13

This core allows you to embed a full-speed (12Mbps) USB 2.0 device core into your FPGA design. The core requires a reasonably precise 48MHz clock. You'd better derive it from a crystal oscillator.



Related Projects

hdl - HDL libraries and projects

  •    Verilog

Analog Devices Inc. HDL libraries and projects. This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.

oh - Silicon proven Verilog library for IC and FPGA designers

  •    Verilog

OH! is an open-source library of hardware building blocks based on silicon proven design practices at 0.35um to 28nm. The library is being used by Adapteva in designing its next generation ASIC. The library is written in standard Verilog (2005) and contains over 25,000 lines of Verilog code, over 150 separate modules. Examples of functionality include: FIFOs, SPI (master/slave), GPIO, high speed links, memories, clock circuits, synchronization primitives,interrupt controller, DMA.

FPGA C Compiler

  •    C

FpgaC compiles a subset of the C language to net lists which can be imported into an FPGA vendors tool chains. C provides an excellent alternative to VHDL/Verilog for algorithmic expression of FPGA reconfigurable computing tasks. More info in wiki.

icestudio - :snowflake: Visual editor for open FPGA boards

  •    Javascript

Visual editor for open FPGA boards. Built on top of the Icestorm project using Apio. Check the Documentation for more information.

FPGA-Litecoin-Miner - A litecoin scrypt miner implemented with FPGA on-chip memory.

  •    Verilog

A litecoin scrypt miner implemented with FPGA on-chip memory.

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

  •    Assembly

For commercial support, please contact The following numbers were obtained by synthesizing the CPU as toplevel without any specific synthesis options to save area or to get better maximal frequency (neutral). The clock constraint is set to an unattainable value, which tends to increase the design area. The dhrystone benchmark was compiled with the -O3 -fno-inline option. All the cached configurations have some cache trashing during the dhrystone benchmark except the VexRiscv full max perf one. This of course reduces the performance. It is possible to produce dhrystone binaries which fit inside a 4KB I$ and 4KB D$ (I already had this case once) but currently it isn't the case. The CPU configurations used below can be found in the src/scala/vexriscv/demo directory.

NyuziProcessor - GPGPU microprocessor architecture

  •    C++

Nyuzi is an experimental GPGPU processor hardware design focused on compute intensive tasks. It is optimized for use cases like blockchain mining, deep learning, and autonomous driving. This project includes a synthesizable hardware design written in System Verilog, an instruction set emulator, an LLVM based C/C++ compiler, software libraries, and tests. It can be used to experiment with microarchitectural and instruction set design tradeoffs.

Rapid HDL


Rapid Hardware Definition Language (Rapid HDL) is an object oriented C# software library in to script/generate/build synthesizable Verilog for FPGA hardware and software co-design in Visual Studio. It also integrates and automates Xilinx or Mentor Graphics build tools.

Groundhog - Serial ATA Host Bus Adapter


Groundhog implements a SATA host bus adapter. This Verilog-based project creates an easy-to-use interface between a user circuit on a Xilinx FPGA and a SATA hard drive or SSD.


  •    C

OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.

aws-fpga - Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

  •    VHDL

The AWS EC2 FPGA Hardware and Software Development Kits include two portions: Development workflows for developing Amazon FPGA Image (AFI) with the HDK or the GUI workflow, and SDK for using AFIs on FPGA-enabled EC2 instances such as F1.The Release Notes document covers the list of supported features, programming environments, and known restrictions.

freedom - Source files for SiFive's Freedom platforms

  •    Scala

This repository contains the RTL created by SiFive for its Freedom E300 and U500 platforms. The Freedom E310 Arty FPGA Dev Kit implements the Freedom E300 Platform and is designed to be mapped onto an Arty FPGA Evaluation Kit. The Freedom U500 VC707 FPGA Dev Kit implements the Freedom U500 Platform and is designed to be mapped onto a VC707 FPGA Evaluation Kit. Both systems boot autonomously and can be controlled via an external debugger. Please read the section corresponding to the kit you are interested in for instructions on how to use this repo.

Source Navigator for Verilog

  •    Perl

Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language.

GPL Cver


Open-source interpreted Verilog simulator with a feature set and performance similar to Verilog-XL. Implements all IEEE 1364-1995 features along with some Verilog-2001 features. Full support for Verilog PLIs.

cello - Genetic circuit design automation

  •    Java

The Cello input is a high-level logic specification written in Verilog, a hardware description language. The code is parsed to generate a truth table, and logic synthesis produces a circuit diagram with the genetically available gate types to implement the truth table. The gates in the circuit are assigned using experimentally characterized genetic gates. In assignment, a predicted circuit score guides a breadth-first search, or a Monte Carlo simulated annealing search. The assignment with the highest score is chosen, and this assignment can be physically implemented in a combinatorial number of different genetic layouts. The Eugene language is used for rule-based constrained combinatorial design of one or more final DNA sequence(s) for the designed circuit. Verilog programs start with a module keyword, followed by the module name, followed by the list of output and input wire names. Within a module definition, Cello currently parses three forms of Verilog: case statements, assign statements, and structural elements (examples below). Verilog code can be entered using a text editor and saved with a .v extension.

ANUBIS Crypto Engine (Verilog)


This is a hardware crypto engine for the Anubis block cipher written in Verilog.


  •    Perl

VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.

Verilog Tool Framework


vrq is verilog parser that supports plugin tools to process verilog. Current plugins include tools to perform x-propagation and to auto build hiearchy.

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