usbcorev - A full-speed device-side USB peripheral core written in Verilog.

  •        13

This core allows you to embed a full-speed (12Mbps) USB 2.0 device core into your FPGA design. The core requires a reasonably precise 48MHz clock. You'd better derive it from a crystal oscillator.

https://github.com/avakar/usbcorev

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