PothosZynq - DMA source and sink blocks for Xilinx Zynq FPGAs

•    VHDL

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DMA source and sink blocks for Xilinx Zynq FPGAs

pothos zynq dma fpga xilinx vivado pothos-framework

RapidWright - Build Customized FPGA Implementations for Vivado

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The RapidWright repository has been retired, effective immediately. The future availability of part of the repository in source format is being reviewed. Subject to these issues being resolved, we hope to re-launch an updated RapidWright repository. We are disappointed by this development and apologize for any inconvenience that it may cause to the community.

xilinx rapidwright fpga vivado

logic - CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs

•    SystemVerilog

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CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado

virtio - Virtio implementation in SystemVerilog

•    SystemVerilog

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Virtio implementation in SystemVerilog.

verilog systemverilog hdl rtl cmake verilator virtio quartus fpga xilinx vivado model systemc

red-pitaya-notes - Notes on the Red Pitaya Open Source Instrument

•    C

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Notes on the Red Pitaya Open Source Instrument

dsp fpga mca nmr radio red-pitaya redpitaya sdr verilog vivado vna wspr xilinx zynq