DMA source and sink blocks for Xilinx Zynq FPGAs
pothos zynq dma fpga xilinx vivado pothos-frameworkThe RapidWright repository has been retired, effective immediately. The future availability of part of the repository in source format is being reviewed. Subject to these issues being resolved, we hope to re-launch an updated RapidWright repository. We are disappointed by this development and apologize for any inconvenience that it may cause to the community.
xilinx rapidwright fpga vivadoCMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado
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