Displaying 1 to 20 from 21 results

atom-beautify - :lipstick: Universal beautification package for Atom editor (:warning: Currently migrating to https://github

  •    CoffeeScript

Atom-Beautify respects the core.telemetryConsent configuration option from Atom editor. If you do not wish to have usage data sent to Google Analytics then please set core.telemetryConsent to no or undecided option before using Atom-Beautify. See Anonymous Analytics section of docs for details. Thank you. Atom-Beautify is going to be completely rewritten with Unibeautify at its core! See unibeautify branch for work in progress and Issue #1174.

ghdl - VHDL 2008/93/87 simulator

  •    VHDL

A new GitHub organization was created (2017-12-20) and the main repo was moved from github.com/tgingold/ghdl to github.com/ghdl/ghdl. Old refs will continue working, because permanent redirects are set up. However, we suggest every contributor to update the remote URLs in their local clones. See Changing a remote's URL. This directory contains the sources of GHDL, the open-source compiler and simulator for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyse and elaborate sources to generate machine code from your design. Native program execution is the only way for high speed simulation.

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

  •    Assembly

For commercial support, please contact spinalhdl@gmail.com. The following numbers were obtained by synthesizing the CPU as toplevel without any specific synthesis options to save area or to get better maximal frequency (neutral). The clock constraint is set to an unattainable value, which tends to increase the design area. The dhrystone benchmark was compiled with the -O3 -fno-inline option. All the cached configurations have some cache trashing during the dhrystone benchmark except the VexRiscv full max perf one. This of course reduces the performance. It is possible to produce dhrystone binaries which fit inside a 4KB I$ and 4KB D$ (I already had this case once) but currently it isn't the case. The CPU configurations used below can be found in the src/scala/vexriscv/demo directory.

vunit - VUnit is a unit testing framework for VHDL/SystemVerilog

  •    VHDL

VUnit is an open source unit testing framework for VHDL/SystemVerilog released under the terms of Mozilla Public License, v. 2.0. It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn't replace but rather complements traditional testing methodologies by supporting a "test early and often" approach through automation. Contributing in the form of code, feedback, ideas or bug reports are welcome. Read our contribution guide to get started.




SECURE_HASH - SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera)

  •    VHDL

SHA-1,SHA-256,SHA-512を計算する論理合成可能なVHDLモジュールです. 1クロックで1、2ワード(1ワードはSHA-1およびSHA-256で32bit、SHA-512では64bit)処理できます.

keyboard-ip - PS/2 Keyboard IP written in VHDL for Xilinx FPGA

  •    VHDL

This PS/2 Keyboard IP is to be used with Xilinx FPGA, as it uses FIFO generated from ISE cores. It is written in VHDL.

potato - A simple RISC-V processor for use in FPGA designs.

  •    VHDL

Note that the master branch may be in an unstable state. Use one of the releases to avoid problems when compiling the code. The Potato Processor is a simple RISC-V processor for use in FPGAs. It implements the 32-bit integer subset of the RISC-V specification version 2.0 and supports the machine mode and the Mbare addressing environment of the RISC-V privileged architecture, version 1.7.

ipxact2systemverilog - Translates IPXACT XML to synthesizable VHDL or SystemVerilog

  •    Python

This software takes an IP-XACT description of register banks, and generates synthesizable VHDL and SystemVerilog packages and ReStructuredText documents. It ONLY considers register bank descriptions. The software does not generate OVM or UVM testbench packages. In the example/tb directory there is an example of how to use the generated packages. You can use http://rst2pdf.ralsina.me to make a pdf from the generated reStructuredText. You can use http://pandoc.org/demos.html to convert to almost any fileformat.


space-invaders-vhdl - Space Invaders game implemented with VHDL

  •    VHDL

This is a simple implementation of Space Invaders in VHDL. To change between screens, press 5 or space.

SpinalHDL - SpinalHDL core

  •    Scala

Also, SpinalHDL is provided "as is", without warranty of any kind.

yavhdl - Yet Another VHDL tool

  •    Yacc

This is yet another attempt to build an open-source VHDL (IEEE 1076-2008) tool that performs parsing, semantic analysis, and elaboration. The goal is to at some point in the future integrate this with the yosys HDL synthesis tool. The initial parser is complete. Semantic analysis is being brainstormed.

riscv_vhdl - VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".

  •    Verilog

This repository provides open source System-on-Chip implementation based on 64-bits CPU "Rocket-chip" distributed under BSD license. SOC source files either include general set of peripheries, FPGA CADs projects files, own implementation of the Windows/Linux debugger and several examples that help to run your firmware on almost any FPGA boards. Satellite Navigation (GPS/GLONASS/Galileo) modules were stubbed in this repository and can be requested on gnss-sensor.com. RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

PoC - IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

  •    VHDL

PoC - “Pile of Cores” provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs. All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and constants. Additionally, a set of simulation helper packages eases the writing of testbenches. Because PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a clear hierachy.

PoC-Examples - This repository contains synthesizable examples which use the PoC-Library.

  •    VHDL

PoC - “Pile of Cores” provides implementations for often required hardware functions such as FIFOs, RAM wrapper, and ALUs. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs. This repository provides common examples and synthesis tests to show how the PoC-Library can be used. The PoC-Library is referenced as a git submodule.

getting-started - List of ideas for getting started with TimVideos projects

  •    Shell

This repository is only used for the GitHub issue tracker. We are very happy to work with students who wish to contribute to the TimVideos project as part of their university course work (and happy to fill out the required paper work).

JSON-for-VHDL - A JSON library implemented in VHDL.

  •    VHDL

JSON-for-VHDL is a library to parse and query JSON data structures in VHDL. The complete functionality is hosted in a single VHDL package, without special dependencies. The JSON-for-VHDL library can be used to parse and query JSON data structures, which are read from disk. The data structure is read via VHDL file I/O functions and procedures and parsed into a internal compressed representation. While the parsing is done, a lightwight index is created to ease the navigation on the data structure.

PicoBlaze-Library - The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA)

  •    VHDL

The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA). The PicoBlaze-Library can be downloaded as a zip-file (latest 'master' branch) or cloned with git clone from GitHub. GitHub offers HTTPS and SSH as transfer protocols. See the Download wiki page for more details.

pyVHDLParser - Streaming based VHDL parser.

  •    Python

This is a token-stream based parser for VHDL-2008.

Learning - My training and testing repository :books:

  •    C++

I am person who spent his life on code and this is what I have after many years of life ... My personal learning code from C, Assembly, Python, ... collected here. some of these code collected from my stackoverflow answers. You can use these example as tutorial.

Cache - Simple implementation of cache using VHDL

  •    VHDL

This project is intended to create a sample and simple implementation of the cache and RAM using VHDL. This code is compiled using GHDL - the open source compiler for VHDL.