Displaying 1 to 9 from 9 results

atom-beautify - :lipstick: Universal beautification package for Atom editor (:warning: Currently migrating to https://github

  •    CoffeeScript

Atom-Beautify respects the core.telemetryConsent configuration option from Atom editor. If you do not wish to have usage data sent to Google Analytics then please set core.telemetryConsent to no or undecided option before using Atom-Beautify. See Anonymous Analytics section of docs for details. Thank you. Atom-Beautify is going to be completely rewritten with Unibeautify at its core! See unibeautify branch for work in progress and Issue #1174.

wavedrom - :ocean: Digital timing diagram rendering engine

  •    Javascript

WaveDrom is a Free and Open Source online digital timing diagram (waveform) rendering engine that uses javascript, HTML5 and SVG to convert a WaveJSON input text description into SVG vector graphics. WaveJSON is an application of the JSON format. The purpose of WaveJSON is to provide a compact exchange format for digital timing diagrams utilized by digital HW / IC engineers.

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

  •    Assembly

For commercial support, please contact spinalhdl@gmail.com. The following numbers were obtained by synthesizing the CPU as toplevel without any specific synthesis options to save area or to get better maximal frequency (neutral). The clock constraint is set to an unattainable value, which tends to increase the design area. The dhrystone benchmark was compiled with the -O3 -fno-inline option. All the cached configurations have some cache trashing during the dhrystone benchmark except the VexRiscv full max perf one. This of course reduces the performance. It is possible to produce dhrystone binaries which fit inside a 4KB I$ and 4KB D$ (I already had this case once) but currently it isn't the case. The CPU configurations used below can be found in the src/scala/vexriscv/demo directory.

usbcorev - A full-speed device-side USB peripheral core written in Verilog.

  •    Verilog

This core allows you to embed a full-speed (12Mbps) USB 2.0 device core into your FPGA design. The core requires a reasonably precise 48MHz clock. You'd better derive it from a crystal oscillator.




pdp6 - PDP-6 Emulator and Verilog Simulation

  •    C

This project aims to revive the PDP-6 (and later PDP-10) computers by DEC. I started by writing a very low level emulator in C based on the schematics. Later I also wrote an accurate verilog simulation that also works on an FPGA.