NyuziProcessor - GPGPU microprocessor architecture

•    C++

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Nyuzi is an experimental GPGPU processor hardware design focused on compute intensive tasks. It is optimized for use cases like blockchain mining, deep learning, and autonomous driving. This project includes a synthesizable hardware design written in System Verilog, an instruction set emulator, an LLVM based C/C++ compiler, software libraries, and tests. It can be used to experiment with microarchitectural and instruction set design tradeoffs.

fpga gpu-computing gpu verilog hardware microprocessor graphics processor-architecture

platformio-core - An open source ecosystem for IoT development :alien: Cross-platform IDE and unified debugger

•    Python

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PlatformIO is an open source ecosystem for IoT development. Cross-platform IDE and unified debugger. Remote unit testing and firmware updates. See contributing guidelines.

iot embedded arduino mbed esp8266 esp32 fpga firmware continuous-integration cloud-ide avr arm platformio ide unit-testing hardware verilog microcontroller debug

atom-beautify - :lipstick: Universal beautification package for Atom editor (:warning: Currently migrating to https://github

•    CoffeeScript

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Atom-Beautify respects the core.telemetryConsent configuration option from Atom editor. If you do not wish to have usage data sent to Google Analytics then please set core.telemetryConsent to no or undecided option before using Atom-Beautify. See Anonymous Analytics section of docs for details. Thank you. Atom-Beautify is going to be completely rewritten with Unibeautify at its core! See unibeautify branch for work in progress and Issue #1174.

atom beautifier formatter coffeescript beautify prettifier prettify js-beautify format pretty html handlebars mustache xml css json sass scss less sql markdown typescript cpp c-sharp coldfusion uncrustify apex pawn vala erb editorconfig yaml front-matter jekyll marko svg elm arduino crystal csv ejs gherkin haskell hindent brittany jade jsx latex ocaml puppet riot.js spacebars swig tss twig visualforce xtemplate autopep8 coffee-formatter coffee-fmt clang-format dfmt elm-format html-beautifier csscomb gherkin-formatter gofmt latex-beautify fortran-beautifier jscs-fixer eslint eslint-fixer lua-beautifier ocp-indent perltidy php-cs-fixer phpcbf pretty-diff pug-beautify puppet-lint r remark rubocop ruby-beautify rustfmt sqlformat stylish-haskell tidy-markdown typescript-formatter yapf erl_tidy marko-beautifier vue vue-beautifier sassconvert formatr clojure-beautifier nunjucks ux-markup pybeautifier cljfmt bash beautysh glsl hh_format nginx nginx-beautify golang-template align-yaml goimports terraform terraformfmt tsx prettier verilog emacs-verilog-mode vhdl vhdl-beautifier gn blade

openwifi - open-source IEEE802.11/Wi-Fi baseband chip/FPGA design

•    C

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openwifi: Linux mac80211 compatible full-stack IEEE802.11/Wi-Fi design based on SDR (Software Defined Radio). This repository includes Linux driver and software. openwifi-hw repository has the FPGA design. It is YOUR RESPONSIBILITY to follow your LOCAL SPECTRUM REGULATION or use CABLE to avoid potential interference over the air.

fpga zynq hls wifi verilog xilinx sdr analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 802-11 mac80211 openwifi

wavedrom - :ocean: Digital timing diagram rendering engine

•    Javascript

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WaveDrom is a Free and Open Source online digital timing diagram (waveform) rendering engine that uses javascript, HTML5 and SVG to convert a WaveJSON input text description into SVG vector graphics. WaveJSON is an application of the JSON format. The purpose of WaveJSON is to provide a compact exchange format for digital timing diagrams utilized by digital HW / IC engineers.

svg diagram waveform verilog rtl

chisel3 - Chisel 3

•    Scala

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Chisel is a new hardware construction language to support advanced hardware design and circuit generation. The latest iteration of Chisel is Chisel3, which uses Firrtl as an intermediate hardware representation language. Chisel3 releases are available as jars on Sonatype/Nexus/Maven and as tagged branches on the releases tab of this repository. The latest release is 3.1.2.

chisel chisel3 firrtl rtl chip-generator verilog

platformio-atom-ide - PlatformIO IDE for Atom: The next generation integrated development environment for IoT

•    Javascript

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Official PlatformIO IDE for IoT, Arduino, ARM mbed, Espressif (ESP8266/ESP32), STM32, PIC32, nRF51/nRF52, FPGA, CMSIS, SPL, AVR, Samsung ARTIK, libOpenCM3

arduino iot atom build esp32 esp8266 libraries embedded ide platformio verilog fpga lattice hardware mbed microcontroller debugger unittest flash firmware avr arm serial monitor

icestudio - :snowflake: Visual editor for open FPGA boards

•    Javascript

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Visual editor for open FPGA boards. Built on top of the Icestorm project using Apio. Check the Documentation for more information.

editor fpga blocks icestorm lattice verilog ide icestudio

hdl - HDL libraries and projects

•    Verilog

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Analog Devices Inc. HDL libraries and projects. This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.

analog-devices hdl jesd204b verilog fpga

e200_opensource - The Ultra-Low Power RISC Core

•    Verilog

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This repository hosts the project for open-source hummingbird E200 RISC processor Core. The Hummingbird E200 core is a two-stages pipeline based ultra-low power/area implementation, which has both performance and areas benchmark better than ARM Cortex-M0+ core, makes the Hummingbird E200 as a perfect replacement for legacy 8051 core or ARM Cortex-M cores in the IoT or other ultra-low power applications.

risc-v ultra-low-power cpu core china verilog

ANUBIS Crypto Engine (Verilog)

•    

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This is a hardware crypto engine for the Anubis block cipher written in Verilog.

anubis-cipher block-cipher cryptography hardware verilog

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

•    Assembly

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For commercial support, please contact spinalhdl@gmail.com. The following numbers were obtained by synthesizing the CPU as toplevel without any specific synthesis options to save area or to get better maximal frequency (neutral). The clock constraint is set to an unattainable value, which tends to increase the design area. The dhrystone benchmark was compiled with the -O3 -fno-inline option. All the cached configurations have some cache trashing during the dhrystone benchmark except the VexRiscv full max perf one. This of course reduces the performance. It is possible to produce dhrystone binaries which fit inside a 4KB I$ and 4KB D$ (I already had this case once) but currently it isn't the case. The CPU configurations used below can be found in the src/scala/vexriscv/demo directory.

riscv soc cpu spinalhdl vhdl verilog fpga softcore

openwifi-hw - FPGA/hardware design of openwifi

•    Verilog

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openwifi: Linux mac80211 compatible full-stack IEEE802.11/Wi-Fi design based on SDR (Software Defined Radio). This repository includes Hardware/FPGA design. To be used together with openwifi driver and software repository.

fpga zynq hls verilog xilinx sdr vivado wi-fi analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 802-11 mac80211 openwifi

Atalanta - Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University

•    Verilog

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Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

atalanta verilog vlsi atpg

LispMicrocontroller - A microcontroller that natively executes a simple LISP dialect

•    Python

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This is a simple microcontroller that runs a compiled LISP dialect. Details of operation are in the wiki. The test runner searches files for patterns that begin with 'CHECK:'. The output of the program will be compared to whatever comes after this declaration. If they do not match, an error will be flagged.

lisp fpga cpu verilog hardware microcontroller

PASC - Parallel Array of Simple Cores. Multicore processor.

•    Verilog

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This is a multi-core embedded processor. There are a 16 RISC cores, each with a small chunk of local memory and a shared global memory area. Documentation is in the wiki (https://github.com/jbush001/PASC/wiki). Replace 'sourcefile' in the command line with the desired file.

verilog fpga cpu processor multicore

usbcorev - A full-speed device-side USB peripheral core written in Verilog.

•    Verilog

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This core allows you to embed a full-speed (12Mbps) USB 2.0 device core into your FPGA design. The core requires a reasonably precise 48MHz clock. You'd better derive it from a crystal oscillator.

fpga verilog usb

mor1kx - mor1kx - an OpenRISC 1000 processor IP core

•    Verilog

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This repository contains an OpenRISC 1000 compliant processor IP core. It is written in Verilog HDL.

verilog openrisc

nybbleForth - Stack machine with 4-bit instructions

•    Forth

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Stack machine with 4-bit instructions. There's a simulator, an assembler, a cross compiler, and a Forth kernel, all written in Forth. There's a hardware design written in Verilog.

forth virtual-machine simulator stack-machine assembler verilog cross-compiler fpga

apple-one - An attempt at a small Verilog implementation of the original Apple 1 on an FPGA

•    Verilog

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This project borrows heavily from the awesome work of Andrew Holme and his "Pool" project and Arlet Otten's tiny 6502 core. Also many special thanks to "sbprojects.com" for the wealth of information I gleaned from there. You can swap out the Basic ROM to get more RAM if you need the space, this can be achieved easily with only minor modifications to the top file.

apple apple1 retrocomputing verilog ice40 terasic-de0 ice40hx8k upduino