Displaying 1 to 20 from 61 results

NyuziProcessor - GPGPU microprocessor architecture

  •    C++

Nyuzi is an experimental GPGPU processor hardware design focused on compute intensive tasks. It is optimized for use cases like blockchain mining, deep learning, and autonomous driving. This project includes a synthesizable hardware design written in System Verilog, an instruction set emulator, an LLVM based C/C++ compiler, software libraries, and tests. It can be used to experiment with microarchitectural and instruction set design tradeoffs.

atom-beautify - :lipstick: Universal beautification package for Atom editor (:warning: Currently migrating to https://github

  •    CoffeeScript

Atom-Beautify respects the core.telemetryConsent configuration option from Atom editor. If you do not wish to have usage data sent to Google Analytics then please set core.telemetryConsent to no or undecided option before using Atom-Beautify. See Anonymous Analytics section of docs for details. Thank you. Atom-Beautify is going to be completely rewritten with Unibeautify at its core! See unibeautify branch for work in progress and Issue #1174.

wavedrom - :ocean: Digital timing diagram rendering engine

  •    Javascript

WaveDrom is a Free and Open Source online digital timing diagram (waveform) rendering engine that uses javascript, HTML5 and SVG to convert a WaveJSON input text description into SVG vector graphics. WaveJSON is an application of the JSON format. The purpose of WaveJSON is to provide a compact exchange format for digital timing diagrams utilized by digital HW / IC engineers.




chisel3 - Chisel 3

  •    Scala

Chisel is a new hardware construction language to support advanced hardware design and circuit generation. The latest iteration of Chisel is Chisel3, which uses Firrtl as an intermediate hardware representation language. Chisel3 releases are available as jars on Sonatype/Nexus/Maven and as tagged branches on the releases tab of this repository. The latest release is 3.1.2.

icestudio - :snowflake: Visual editor for open FPGA boards

  •    Javascript

Visual editor for open FPGA boards. Built on top of the Icestorm project using Apio. Check the Documentation for more information.

hdl - HDL libraries and projects

  •    Verilog

Analog Devices Inc. HDL libraries and projects. This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.


e200_opensource - The Ultra-Low Power RISC Core

  •    Verilog

This repository hosts the project for open-source hummingbird E200 RISC processor Core. The Hummingbird E200 core is a two-stages pipeline based ultra-low power/area implementation, which has both performance and areas benchmark better than ARM Cortex-M0+ core, makes the Hummingbird E200 as a perfect replacement for legacy 8051 core or ARM Cortex-M cores in the IoT or other ultra-low power applications.

ANUBIS Crypto Engine (Verilog)

  •    

This is a hardware crypto engine for the Anubis block cipher written in Verilog.

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

  •    Assembly

For commercial support, please contact spinalhdl@gmail.com. The following numbers were obtained by synthesizing the CPU as toplevel without any specific synthesis options to save area or to get better maximal frequency (neutral). The clock constraint is set to an unattainable value, which tends to increase the design area. The dhrystone benchmark was compiled with the -O3 -fno-inline option. All the cached configurations have some cache trashing during the dhrystone benchmark except the VexRiscv full max perf one. This of course reduces the performance. It is possible to produce dhrystone binaries which fit inside a 4KB I$ and 4KB D$ (I already had this case once) but currently it isn't the case. The CPU configurations used below can be found in the src/scala/vexriscv/demo directory.

Atalanta - Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University

  •    Verilog

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

LispMicrocontroller - A microcontroller that natively executes a simple LISP dialect

  •    Python

This is a simple microcontroller that runs a compiled LISP dialect. Details of operation are in the wiki. The test runner searches files for patterns that begin with 'CHECK:'. The output of the program will be compared to whatever comes after this declaration. If they do not match, an error will be flagged.

PASC - Parallel Array of Simple Cores. Multicore processor.

  •    Verilog

This is a multi-core embedded processor. There are a 16 RISC cores, each with a small chunk of local memory and a shared global memory area. Documentation is in the wiki (https://github.com/jbush001/PASC/wiki). Replace 'sourcefile' in the command line with the desired file.

usbcorev - A full-speed device-side USB peripheral core written in Verilog.

  •    Verilog

This core allows you to embed a full-speed (12Mbps) USB 2.0 device core into your FPGA design. The core requires a reasonably precise 48MHz clock. You'd better derive it from a crystal oscillator.

mor1kx - mor1kx - an OpenRISC 1000 processor IP core

  •    Verilog

This repository contains an OpenRISC 1000 compliant processor IP core. It is written in Verilog HDL.

nybbleForth - Stack machine with 4-bit instructions

  •    Forth

Stack machine with 4-bit instructions. There's a simulator, an assembler, a cross compiler, and a Forth kernel, all written in Forth. There's a hardware design written in Verilog.

apple-one - An attempt at a small Verilog implementation of the original Apple 1 on an FPGA

  •    Verilog

This project borrows heavily from the awesome work of Andrew Holme and his "Pool" project and Arlet Otten's tiny 6502 core. Also many special thanks to "sbprojects.com" for the wealth of information I gleaned from there. You can swap out the Basic ROM to get more RAM if you need the space, this can be achieved easily with only minor modifications to the top file.

hdl-tools - Facilitates building open source tools for working with hardware description languages (HDLs)

  •    Perl

Environment for working with HDLs. This builds a number of tools from source and relies on some scripts to facilitate HDL work. Tools will, by default, be installed in ./opt/. However, you can pass a PREFIX option to the Makefile if for whatever reason you want to install these somewhere else (not advised).

openofdm - Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

  •    Verilog

See full documentation at http://openofdm.readthedocs.io. In a nutshell, the top level dot11 Verilog module takes 32-bit I/Q samples (16-bit each) as input, and output decoded bytes in 802.11 packet. The sampling rate is 20 MSPS and the clock rate is 100 MHz. This means this module expects one pair of I/Q sample every 5 clock ticks.