Displaying 1 to 11 from 11 results

awilix - Extremely powerful Inversion of Control (IoC) container for Node.JS

  •    TypeScript

That example is rather lengthy, but if you extract things to their proper files it becomes more manageable.

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

  •    Assembly

For commercial support, please contact spinalhdl@gmail.com. The following numbers were obtained by synthesizing the CPU as toplevel without any specific synthesis options to save area or to get better maximal frequency (neutral). The clock constraint is set to an unattainable value, which tends to increase the design area. The dhrystone benchmark was compiled with the -O3 -fno-inline option. All the cached configurations have some cache trashing during the dhrystone benchmark except the VexRiscv full max perf one. This of course reduces the performance. It is possible to produce dhrystone binaries which fit inside a 4KB I$ and 4KB D$ (I already had this case once) but currently it isn't the case. The CPU configurations used below can be found in the src/scala/vexriscv/demo directory.

vast - :crystal_ball: Visibility Across Space and Time – The network telemetry engine for data-driven security investigations

  •    C++

The network telemetry engine for data-driven security investigations. High-Throughput Ingestion: import numerous log formats over 100k events/second, including Zeek, Suricata, JSON, and CSV.

bookmarks-frontend - A bookmark application, front end part

  •    Javascript

It's a typical front end project you can start working on without feel shame. It's recommended that start a gulp watch in a terminal, and launch the sinatra in another one.

riscv_vhdl - VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".

  •    Verilog

This repository provides open source System-on-Chip implementation based on 64-bits CPU "Rocket-chip" distributed under BSD license. SOC source files either include general set of peripheries, FPGA CADs projects files, own implementation of the Windows/Linux debugger and several examples that help to run your firmware on almost any FPGA boards. Satellite Navigation (GPS/GLONASS/Galileo) modules were stubbed in this repository and can be requested on gnss-sensor.com. RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

PicoBlaze-Library - The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA)

  •    VHDL

The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA). The PicoBlaze-Library can be downloaded as a zip-file (latest 'master' branch) or cloned with git clone from GitHub. GitHub offers HTTPS and SSH as transfer protocols. See the Download wiki page for more details.

THRecon - Threat Hunting Reconnaissance Toolkit

  •    PowerShell

Collect endpoint information for use in incident response, threat hunting, live forensics, baseline monitoring, etc. * Info pulled from current running processes or their executables on disk.

cyberops - Cisco Press CCNA Cyber Ops Books and Video Courses supplemental information and additional study materials


Cisco Press CCNA CyberOps Books and Video Courses supplemental information and additional study materials. Whether you are preparing for the CCNA Cyber Ops certification or just changing careers to cyber security, this book will help you gain the knowledge you need to get started and prepared. When writing this book, we did so with you in mind, and together we will discover the critical ingredients that make up the recipe for a secure network and how to succeed in cyber security operations. By focusing on covering the objectives for the CCNA Cyber Ops SECFND exam and integrating that with real-world best practices and examples, we created this content with the intention of being your personal tour guides as we take you on a journey through the world of network security.

PatrowlHears - PatrowlHears - Vulnerability Intelligence Center / Exploits

  •    Python

PatrOwl provides scalable, free and open-source solutions for orchestrating Security Operations and providing Threat Intelligence feeds. PatrowlHears is an advanced and real-time Vulnerability Intelligence platform, including CVE, exploits and threats news. To try PatrowlHears, install it by reading the Installation Guide.

Vitis_Accel_Examples - Vitis_Accel_Examples

  •    C++

Welcome to the Vitis Accel Examples' repository. This repository contains examples to showcase various features of the Vitis tools and platforms. It is expected that users have gone through the tutorials and have developed a basic understanding of the tools and the programming model. This repository illustrates specific scenarios related to host code and kernel programming through small working examples. The intention is for users to be able to use these working examples as a reference while developing their own accelerator application based on Xilinx platforms.

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