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awesome-cpus - All CPU and MCU documentation in one place
This repository contains documentation for various CPUs. There are data sheets, programmer's manuals, quick reference cards, etc. Before submitting a pull request, please read the Contribution Guidelines.
cpu avr openrisc mcu vax xtensa microblaze datasheet sparc powerpc z80 pdp-10 pdp-11 pdp-1 pdp-8 arm m68k risc-v i860 i960RT-Thread - A Tiny and Elegant IoT Operating System
RT-Thread (Real-Time Thread) is an open source embedded real-time operating system. It has a strong scalability: from a nano kernel running on a tiny MCU, for example ARM Cortex-M0, or Cortex-M¾/7, to a rich feature system running on MIPS32, ARM Cortex-A, even the emerging open source RISC-V architecture is supported. RT-Thread can run either on single-core systems or on symmetric multi-core processors(SMP) systems.
rtos cortex-m iot arm mips kernel embedded-systems china cortex-a esp32 xtensa risc-v andes operating-system real-time-operating-systemibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Ibex is a production-quality open source 32-bit RISC-V CPU core written in SystemVerilog. The CPU core is heavily parametrizable and well suited for embedded control applications. Ibex is being extensively verified and has seen multiple tape-outs. Ibex supports the Integer (I) or Embedded (E), Integer Multiplication and Division (M), Compressed (C), and B (Bit Manipulation) extensions. The block diagram below shows the small parametrization with a 2-stage pipeline.
hardware risc-v rv32 cpucoreeclipse-plugins - The GNU MCU Eclipse plug-ins for ARM & RISC-V C/C++ developers
These are the Eclipse projects used to build the GNU MCU Eclipse plug-ins. For new installs, the preferred method is via GNU MCU Eclipse IDE for C/C++ Developers , which packs the official Eclipse IDE for C/C++ Developers release with all GNU MCU Eclipse plug-ins already installed.
eclipse arm risc-v pluginse200_opensource - The Ultra-Low Power RISC Core
This repository hosts the project for open-source hummingbird E200 RISC processor Core. The Hummingbird E200 core is a two-stages pipeline based ultra-low power/area implementation, which has both performance and areas benchmark better than ARM Cortex-M0+ core, makes the Hummingbird E200 as a perfect replacement for legacy 8051 core or ARM Cortex-M cores in the IoT or other ultra-low power applications.
risc-v ultra-low-power cpu core china verilogpotato - A simple RISC-V processor for use in FPGA designs.
Note that the master branch may be in an unstable state. Use one of the releases to avoid problems when compiling the code. The Potato Processor is a simple RISC-V processor for use in FPGAs. It implements the 32-bit integer subset of the RISC-V specification version 2.0 and supports the machine mode and the Mbare addressing environment of the RISC-V privileged architecture, version 1.7.
processor risc-v vhdllbForth - Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm
This is a self-hosted implementation of Forth, which can regenerate itself from Forth source code. The bootstrapping process uses a metacompiler written in Lisp to target a small inner interpreter and a handful of code words written in C. A new metacompiler written in Forth generates an x86 executable using using assembly language code words. There are also ARM, RISC-V, Motorola 68000, PDP-11, and asm.js targets. There is a cross compiler for 6502, 8051, AVR, Cortex-M, MSP430, PDP-8, PIC, and STM8.
forth compiler interpreter metacompiler pdp11 m68k self-hosted arm programming-language x86 asmjs risc-v riscv 6502 msp430 avr 8051 cortex-micicle - 32-bit RISC-V system on chip for iCE40 FPGAs
Icicle is a 32-bit RISC-V system on chip for iCE40 HX8K and iCE40 UP5K FPGAs. It can be built with the open-source Project IceStorm toolchain and currently targets the iCE40-HX8K breakout board, with experimental support for the UPduino board. The make stat target runs icebox_stat and the make time target prints the icetime report.
risc-v ice40 fpga icestormgrift - Galois RISC-V ISA Formal Tools
Galois RISC-V ISA Formal Tools (hereafter, GRIFT) is part of the BESSPIN software suite, developed by Galois, Inc. It contains a concrete representation of the semantics of the RISC-V instruction set, along with an elegant encoding/decoding mechanism, and simulation and analysis front-ends. It is intended for broad use in the RISC-V community - simulation, binary analysis, and software & hardware verification/validation are all current and/or potential future uses for GRIFT, and we have designed it specifically with these broad application domains in mind. GRIFT differs from other Haskell-based RISC-V formalizations in its coding style (using highly dependently-typed GHC Haskell) and some of its foundational design decisions. Its primary use is as a library, providing mechanisms for the encoding/decoding of instructions, as well as running RISC-V programs in simulation. However, the semantics of the instructions themselves are represented, not as Haskell functions on a RISC-V machine state (registers, PC, memory, etc.), but as symbolic expressions in a general-purpose bitvector expression language. This extra layer of representation, while sub-optimal for fast simulation, facilitates the library's use as a general-purpose encoding of the semantics, and makes GRIFT a general-purpose, "golden reference" model that can be easily translated into the syntax of other tools by providing minimal pretty printers, written in Haskell, for the underlying bitvector expression language. Having explicit semantic data for each instruction also facilitates the library's incorporation with other Haskell-based tooling, such as coverage analysis (where a notion of coverage is encoded in the same bitvector language as the semantics), binary analysis, and verification, both within and without the Haskell programming environment.
risc-v formal-methods formal-specification simulationgetting-started - List of ideas for getting started with TimVideos projects
This repository is only used for the GitHub issue tracker. We are very happy to work with students who wish to contribute to the TimVideos project as part of their university course work (and happy to fill out the required paper work).
gsoc gsoc-2016 gsoc-2017 fpga electronics university verilog vhdl projects hdmi video mjpeg usb usb-devices webcam hdmi2usb risc-v or1kparallella-riscv - RISC-V port to Parallella Board
With this project I hope to benefit the open-source hardware enthusiast community with work related to the incredible Parallella board used by thousands of students and hobbyists around the world. This project will focus on the integration of the RISC-V rocket core, inside the Zynq FPGA device of Parallella. The RISC-V rocket core is an implementation of the RISV-V ISA that has gotten a lot of attention and support due to being clean, modular and power efficient. This project will allow owners of Parallella boards to write and execute RISC-V programs with minimal effort from their side. The system will work out of the box with a prebuilt binary image ready to be placed in an SD card and users will be able to re-build it with minimal effort. Moreover, a tutorial document will be created to aid inexperienced users make the most of this work and allow them to modify it for their own needs and purposes with custom hardware and / or software code.
parallella risc-v board-parallella rocket-chip zynq linux-kernel zedboard gsoc gsoc-2016RV12 - RISC-V CPU Core
The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses. It features an optimizing folded 4-stage pipeline, which optimizes overlaps between the execution and memory accesses, thereby reducing stalls and improving efficiency. Requires the Roa Logic Memories IPs and AHB3Lite Package. These are included as submodules.
risc-v 32-bit 64bit cpumeta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
This is the general hardware specific BSP overlay for the RISC-V based devices. Note: You only need this if you do not have an existing Yocto Project build environment.
risc-v riscv yocto yocto-layer yocto-meta openembedded openembedded-layerRISCV_CPU - A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
This project is a FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL, a course project of Computer Architecture(MS108), ACM honor class @ SJTU. This project is a simple five stage pipelined cpu for risc-v (rv32i) written in verilog HDL.
verilog-hdl risc-vbusybear-linux - busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu
busybear-linux is a tiny RISC-V Linux root filesystem image that targets the virt board in riscv-qemu. As the name suggests, busybear-linux is a riscv-linux root image comprised of busybox and dropbear. The root image is intended to demonstrate virtio-net and virtio-block in riscv-qemu and features a dropbear ssh server which allows out-of-the-box ssh access to a RISC-V virtual machine.
risc-v linux-kernel qemu qemu-riscv busybox dropbear busybear riscv-linux virtual-machine virtioriscv-meta - RISC-V Instruction Set Metadata
RISC-V Instruction Set Metadata
risc-v riscv metadata risc
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