Displaying 1 to 20 from 23 results

RE-for-beginners - "Reverse Engineering for Beginners" free book

  •    TeX

Topics discussed: x86/x64, ARM/ARM64, MIPS, Java/JVM. Compiled versions can be found here: English, Russian, German and French.

bap - Binary Analysis Platform

  •    OCaml

The Carnegie Mellon University Binary Analysis Platform (CMU BAP) is a reverse engineering and program analysis platform that works with binary code and doesn't require the source code. BAP supports multiple architectures: ARM, x86, x86-64, PowerPC, and MIPS. BAP disassembles and lifts binary code into the RISC-like BAP Instruction Language (BIL). Program analysis is performed using the BIL representation and is architecture independent in a sense that it will work equally well for all supported architectures. The platform comes with a set of tools, libraries, and plugins. The documentation and tutorial are also available. The main purpose of BAP is to provide a toolkit for implementing automated program analysis. BAP is written in OCaml and it is the preferred language to write analysis, we have bindings to C, Python and Rust. The Primus Framework also provide a Lisp-like DSL for writing program analysis tools. BAP is developed in CMU, Cylab and is sponsored by various grants from the United States Department of Defense, Siemens AG, and the Korea government, see sponsors for more information.

capstone - Capstone disassembly/disassembler framework: Core (Arm, Arm64, EVM, M68K, M680X, Mips, PPC, Sparc, SystemZ, TMS320C64x, X86, X86_64, XCore) + bindings (Python, Java, Ocaml, PowerShell, Visual Basic)

  •    C

Capstone is a disassembly framework with the target of becoming the ultimate disasm engine for binary analysis and reversing in the security community. Support multiple hardware architectures: ARM, ARM64 (ARMv8), Ethereum VM, M68K, Mips, PPC, Sparc, SystemZ, TMS320C64X, M680X, XCore and X86 (including X86_64).

RT-Thread - A Tiny and Elegant IoT Operating System

  •    C

RT-Thread (Real-Time Thread) is an open source embedded real-time operating system. It has a strong scalability: from a nano kernel running on a tiny MCU, for example ARM Cortex-M0, or Cortex-M¾/7, to a rich feature system running on MIPS32, ARM Cortex-A, even the emerging open source RISC-V architecture is supported. RT-Thread can run either on single-core systems or on symmetric multi-core processors(SMP) systems.

plasma - Plasma is an interactive disassembler for x86/ARM/MIPS

  •    Python

The old project name was Reverse. PLASMA is an interactive disassembler. It can generate a more readable assembly (pseudo code) with colored syntax. You can write scripts with the available Python api (see an example below). The project is still in big development.

steed - [WIP] Rust's standard library, free of C dependencies, for Linux systems

  •    Rust

It's very early days. Very little functionality has been ported over. Should work without having to install a C toolchain or cross compiled C libraries, and without having to run the command inside a Docker container / VM.

cemu - Cheap EMUlator: lightweight multi-architecture assembly playground

  •    Python

Writing assembly is fun. Assembly is the lowest language (humanly understandable) available to communicate with computers, and is crucial to understand the internal mechanisms of any machine. Unfortunately, setting up an environment to write, compile and run assembly for various architectures (x86, ARM, MIPS, SPARC) has always been painful. CEmu is an attempt to fix this by providing a bundled GUI application that empowers users to write assembly and test it by compiling it to bytecode and executing it in an QEMU-based emulator. CEmu combines all the advantages of a basic assembly IDE, compilation and execution environment, by relying on the great libraries Keystone, Unicorn and Capstone engines in a Qt powered GUI.

node-capstone - Node

  •    Javascript

node-capstone provides Node.js bindings for the Capstone disassembler library, allowing binary data in Buffer objects to be disassembled using any of Capstone's supported architectures. On Windows and Linux, install a pre-compiled binary from the Capstone download page, or build from source.

cache-simulator - A processor cache simulator for the MIPS instruction set architecture

  •    Python

This program simulates a processor cache for the MIPS instruction set architecture. It can simulate all three fundamental caching schemes: direct-mapped, n-way set associative, and fully associative. The program must be run from the command line and requires Python 3.4+ to run. Executing the program will run the simulation and print an ASCII table containing the details for each supplied word address, as well as the final contents of the cache.

peasauce - Peasauce Interactive Disassembler

  •    Python

If you wish to generally support or encourage the development of this tool, or sponsor the development of specific features, Paypal donations will be used for that purpose. For those who are serious about sponsoring development of a specific feature it is best to discuss it with me at my email address first. The current primary goal is to handle disassembling Amiga m68000 executables. Support for the wider family of m680x0 instructions, or executables for other platforms that used these chips is within scope, in order to drive better code structure for later expansion to other architectures or platforms.

f32c - A 32-bit RISC-V / MIPS ISA retargetable CPU core

  •    VHDL

f32c is a retargetable, scalar, pipelined, 32-bit processor core which can execute subsets of either RISC-V or MIPS instruction sets. It is implemented in parametrized VHDL which permits synthesis with different area / speed tradeoffs, and includes a branch predictor, exception handling control block, and optional direct-mapped caches. The RTL code also includes SoC modules such as a multi-port SDRAM and SRAM controllers, video framebuffers with composite (PAL), HDMI, DVI and VGA outputs with simple 2D acceleration for sprites and windows, floating point vector processor, SPI, UART, PCM audio, GPIO, PWM outputs and a timer, as well as glue logic tailored for numerous popular FPGA development boards from various manufacturers. In synthetic integer benchmarks the core yields 3.06 CoreMark/MHz and 1.63 DMIPS/MHz (1.81 DMIPS/MHz with function inlining) with code and data stored in on-chip block RAMs. When configured with 16 KB of instruction and 4 KB of data cache, and with code and data stored in external SDRAM, the core yields 2.78 CoreMark/MHz and 1.31 DMIPS/MHz.

spym - MIPS ISA toolchain including a (dis)assembler, debugger, and vm.

  •    Python

A MIPS ISA toolchain including a (dis)assembler, debugger, and runtime. For fun, inside the linux/ directory resides the source for a kernel module that enables native execution of SPYM binaries on Linux.

defcon26_badgehacking - Notes and things regarding hacking DEFCON 26's badge

  •    C

Flash patched firmware to badge using a PIC programmer - see Tymkrs' instructions here. If you use a PICKit3 and don't solder headers, be warned that you'll have to keep good contact with the pads using your fingers for up to a minute. Reset the badge so that you are in the starting room with no actions taken (just pull the power).

NaiveMIPS-HDL - Naïve MIPS32 SoC implementation

  •    Verilog

Naïve MIPS32 SoC implementation

realtek-mips-sdks - Realtek Network SoC/CPU toolchains (including support for Lexra based chips)

  •    C

This package contains various Realtek SDKs (including toolchains) for MIPS based systems. It also includes an 'activate' script that can be sourced from a bash shell. This script makes using the toolchains easier.

mipsasm - MIPS assembler and IDE

  •    Java

This is my project for Computer Organization, Shi Qingsong, Zhejiang University. The MIPS assembler is based on the MIPS 32 specification, with some custom extensions.

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