Displaying 1 to 12 from 12 results

icestudio - :snowflake: Visual editor for open FPGA boards

  •    Javascript

Visual editor for open FPGA boards. Built on top of the Icestorm project using Apio. Check the Documentation for more information.

RSA-and-LLL-attacks - attacking RSA via lattice reductions (LLL)

  •    TeX

This repo host implementations and explanations of different RSA attacks using lattice reduction techniques (in particular LLL). First, we'll see how Coppersmith found out that you could use lattice reduction techniques to attack a relaxed model of RSA (we know parts of the message, or we know parts of one of the prime, ...). And how Howgrave-Graham reformulated his attack.

ggplotify - ggplot everything

  •    R

Convert plot function call (using expression or formula) to 'grob' or 'ggplot' object that compatible to the 'grid' and 'ggplot2' ecosystem. With this package, we are able to e.g. using 'cowplot' to align plots produced by 'base' graphics, 'grid', 'lattice', 'vcd' etc. by converting them to 'ggplot' objects. For more details, please refer to the online vignette.

platform-lattice_ice40 - Lattice iCE40: development platform for PlatformIO

  •    Python

Lattice iCE40 are the first FPGAs fully usable by open source tools. Please navigate to documentation.

apio - :seedling: Open source ecosystem for open FPGA boards

  •    Python

Experimental open source micro-ecosystem for open FPGAs. Based on platformio. Apio is a multiplatform toolbox, with static pre-built packages, project configuration tools and easy commands to verify, synthesize, simulate and upload your verilog designs. Apio is used by Icestudio.

f32c - A 32-bit RISC-V / MIPS ISA retargetable CPU core

  •    VHDL

f32c is a retargetable, scalar, pipelined, 32-bit processor core which can execute subsets of either RISC-V or MIPS instruction sets. It is implemented in parametrized VHDL which permits synthesis with different area / speed tradeoffs, and includes a branch predictor, exception handling control block, and optional direct-mapped caches. The RTL code also includes SoC modules such as a multi-port SDRAM and SRAM controllers, video framebuffers with composite (PAL), HDMI, DVI and VGA outputs with simple 2D acceleration for sprites and windows, floating point vector processor, SPI, UART, PCM audio, GPIO, PWM outputs and a timer, as well as glue logic tailored for numerous popular FPGA development boards from various manufacturers. In synthetic integer benchmarks the core yields 3.06 CoreMark/MHz and 1.63 DMIPS/MHz (1.81 DMIPS/MHz with function inlining) with code and data stored in on-chip block RAMs. When configured with 16 KB of instruction and 4 KB of data cache, and with code and data stored in external SDRAM, the core yields 2.78 CoreMark/MHz and 1.31 DMIPS/MHz.

PoC - IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

  •    VHDL

PoC - “Pile of Cores” provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs. All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and constants. Additionally, a set of simulation helper packages eases the writing of testbenches. Because PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a clear hierachy.

timing_attack_ecdsa_tls - Timing Attack on TLS' ECDSA signature

  •    TeX

This is a work trying to reproduce and improve on Billy Bob Brumley and Nicola Tuveri - Remote Timing Attacks are Still Practical. It works on an unpatched version of OpenSSL, but theorically it should work on any TLS framework that has such a timing attack (and not only on binary curves).

JSON-for-VHDL - A JSON library implemented in VHDL.

  •    VHDL

JSON-for-VHDL is a library to parse and query JSON data structures in VHDL. The complete functionality is hosted in a single VHDL package, without special dependencies. The JSON-for-VHDL library can be used to parse and query JSON data structures, which are read from disk. The data structure is read via VHDL file I/O functions and procedures and parsed into a internal compressed representation. While the parsing is done, a lightwight index is created to ease the navigation on the data structure.

gonano - An implementation of the Nano cryptocurrency in Go

  •    Go

gonano is a WIP implementation of the Nano cryptocurrency in Go. This is a work in progress. Do not use this in production environments. All of the exported API's are subject to change and should thus not be considered stable. The same applies to the database format, configuration files and wallet files.