98 best open source fpga projects.

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Displaying 1 to 20 from 98 results

NyuziProcessor - GPGPU microprocessor architecture

Nyuzi is an experimental GPGPU processor hardware design focused on compute intensive tasks. It is optimized for use cases like blockchain mining, deep learning, and autonomous driving. This project includes a synthesizable hardware design written in System Verilog, an instruction set emulator, an LLVM based C/C++ compiler, software libraries, and tests. It can be used to experiment with microarchitectural and instruction set design tradeoffs.

fpga gpu-computing gpu verilog hardware microprocessor graphics processor-architecture

platformio-core - An open source ecosystem for IoT development :alien: Cross-platform IDE and unified debugger

Python

PlatformIO is an open source ecosystem for IoT development. Cross-platform IDE and unified debugger. Remote unit testing and firmware updates. See contributing guidelines.

iot embedded arduino mbed esp8266 esp32 fpga firmware continuous-integration cloud-ide avr arm platformio ide unit-testing hardware verilog microcontroller debug

paddle-mobile - This research aims at simply deploying deeplearning on mobile and embedded devices, with low complexity and high speed

This research aims at simply deploying deeplearning on mobile and embedded devices, with low complexity and high speed. old name mobile deep learning.

mobile deep-learning neural-network arm mdl baidu embedded mali fpga

openwifi - open-source IEEE802.11/Wi-Fi baseband chip/FPGA design

openwifi: Linux mac80211 compatible full-stack IEEE802.11/Wi-Fi design based on SDR (Software Defined Radio). This repository includes Linux driver and software. openwifi-hw repository has the FPGA design. It is YOUR RESPONSIBILITY to follow your LOCAL SPECTRUM REGULATION or use CABLE to avoid potential interference over the air.

fpga zynq hls wifi verilog xilinx sdr analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 802-11 mac80211 openwifi

Paddle-Lite - Multi-platform high performance deep learning inference engine (『飞桨』多平台高性能深度学习预测引擎）

Multi-platform high performance deep learning inference engine (『飞桨』多平台高性能深度学习预测引擎）

arm mobile embedded fpga deep-learning neural-network mali baidu mdl mobile-deep-learning

platformio-atom-ide - PlatformIO IDE for Atom: The next generation integrated development environment for IoT

Javascript

Official PlatformIO IDE for IoT, Arduino, ARM mbed, Espressif (ESP8266/ESP32), STM32, PIC32, nRF51/nRF52, FPGA, CMSIS, SPL, AVR, Samsung ARTIK, libOpenCM3

arduino iot atom build esp32 esp8266 libraries embedded ide platformio verilog fpga lattice hardware mbed microcontroller debugger unittest flash firmware avr arm serial monitor

icestudio - :snowflake: Visual editor for open FPGA boards

Javascript

Visual editor for open FPGA boards. Built on top of the Icestorm project using Apio. Check the Documentation for more information.

editor fpga blocks icestorm lattice verilog ide icestudio

hdl - HDL libraries and projects

Verilog

Analog Devices Inc. HDL libraries and projects. This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.

analog-devices hdl jesd204b verilog fpga

XRT - Xilinx Run Time for FPGA

Xilinx Runtime (XRT) is implemented as as a combination of userspace and kernel driver components. XRT supports both PCIe based boards like U30, U50, U200, U250, U280, VCK190 and MPSoC based embedded platforms. XRT provides a standardized software interface to Xilinx FPGA. The key user APIs are defined in xrt.h header file.

fpga linux-kernel xrt vitis

brevitas - Brevitas: quantization-aware training in PyTorch

Python

Brevitas is a PyTorch research library for quantization-aware training (QAT). Brevitas is currently under active development. Documentation, examples, and pretrained models will be progressively released.

text-to-speech fpga pytorch speech-recognition neural-networks image-classification xilinx quantization hardware-acceleration brevitas

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

Assembly

For commercial support, please contact spinalhdl@gmail.com. The following numbers were obtained by synthesizing the CPU as toplevel without any specific synthesis options to save area or to get better maximal frequency (neutral). The clock constraint is set to an unattainable value, which tends to increase the design area. The dhrystone benchmark was compiled with the -O3 -fno-inline option. All the cached configurations have some cache trashing during the dhrystone benchmark except the VexRiscv full max perf one. This of course reduces the performance. It is possible to produce dhrystone binaries which fit inside a 4KB I$ and 4KB D$ (I already had this case once) but currently it isn't the case. The CPU configurations used below can be found in the src/scala/vexriscv/demo directory.

riscv soc cpu spinalhdl vhdl verilog fpga softcore

vunit - VUnit is a unit testing framework for VHDL/SystemVerilog

VHDL

VUnit is an open source unit testing framework for VHDL/SystemVerilog released under the terms of Mozilla Public License, v. 2.0. It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn't replace but rather complements traditional testing methodologies by supporting a "test early and often" approach through automation. Contributing in the form of code, feedback, ideas or bug reports are welcome. Read our contribution guide to get started.

vhdl verification systemverilog-hdl unit-testing fpga asic testbench

ariane - Ariane is a 6-stage RISC-V CPU

SystemVerilog

Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M and C extensions as specified in Volume I: User-Level ISA V 2.1 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore it is compliant to the draft external debug spec 0.13. It has configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer and branch history table). The primary design goal was on reducing critical path length.

riscv64imc systemverilog-hdl cpu riscv asic fpga

fusesoc - FuseSoC is a package manager and a set of build tools for FPGA/ASIC development

Python

FuseSoC is an award-winning package manager and a set of build tools for HDL (Hardware Description Language) code. Its main purpose is to increase reuse of IP (Intellectual Property) cores and be an aid for creating, building and simulating SoC solutions.

eda reuse package-manager fpga

openwifi-hw - FPGA/hardware design of openwifi

Verilog

openwifi: Linux mac80211 compatible full-stack IEEE802.11/Wi-Fi design based on SDR (Software Defined Radio). This repository includes Hardware/FPGA design. To be used together with openwifi driver and software repository.

fpga zynq hls verilog xilinx sdr vivado wi-fi analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 802-11 mac80211 openwifi

cfm - A 16-bit CPU and system, written in Haskell and running Forth on FPGA.

Haskell

This is a Forth-inspired processor targeting the Lattice ICE40 FPGA series, primarily targeting the Icoboard. The distribution includes BsForth, a non-ANS Forth implementation that can provide a bare-bones interactive development environment with optimizing compiler in less than 5 kiB. It's interesting in the way that it bootstraps (using the cycle-accurate emulator) and for its machine instruction fusion algorithm.

forth hardware haskell embedded fpga

LispMicrocontroller - A microcontroller that natively executes a simple LISP dialect

Python

This is a simple microcontroller that runs a compiled LISP dialect. Details of operation are in the wiki. The test runner searches files for patterns that begin with 'CHECK:'. The output of the program will be compared to whatever comes after this declaration. If they do not match, an error will be flagged.

lisp fpga cpu verilog hardware microcontroller

PASC - Parallel Array of Simple Cores. Multicore processor.

Verilog

This is a multi-core embedded processor. There are a 16 RISC cores, each with a small chunk of local memory and a shared global memory area. Documentation is in the wiki (https://github.com/jbush001/PASC/wiki). Replace 'sourcefile' in the command line with the desired file.

verilog fpga cpu processor multicore