dblclockfft - A configurable C++ generator of pipelined Verilog FFT cores

  •        6

One sample in per clock, with the i_ce line being high for every incoming sample--up to one sample per clock. There's also options to run with at least one clock between samples, or even two clocks between samples (or more). This mode uses 3, 2, or 1 multiplies per FFT stage respectively. Eventually, I want to support a real FFT mode which will accept real samples input, and alternately produce real and imaginary samples output--or the converse for the inverse FFT.

https://github.com/ZipCPU/dblclockfft

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