riscv-cores-list - RISC-V Cores, SoC platforms and SoCs

  •        5

This document captures the status of various cores and SoCs that endeavor to implement the RISC-V specification. Note that none of these cores/SoCs have passed the in-development RISC-V compliance suite. Please add to the list and fix inaccuracies.

https://riscv.org/risc-v-cores/
https://github.com/riscv/riscv-cores-list

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Related Projects

ariane - Ariane is a 6-stage RISC-V CPU

  •    SystemVerilog

Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M and C extensions as specified in Volume I: User-Level ISA V 2.1 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore it is compliant to the draft external debug spec 0.13. It has configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer and branch history table). The primary design goal was on reducing critical path length.

riscv-boom - Berkeley Out-of-Order Machine

  •    Scala

This is the source repository for the RV64G RISC-V superscalar Berkeley Out-of-Order Machine (BOOM), written in the Chisel hardware construction language. BOOM is a synthesizable core that targets ASIC processes. It can run on an FPGA (50 MHz on a zc706), but optimizing it to be an FPGA soft-core is a non-goal. For documentation on BOOM visit (https://ccelio.github.io/riscv-boom-doc).

riscv-isa-sim - Spike, a RISC-V ISA Simulator

  •    C

Spike, the RISC-V ISA Simulator, implements a functional model of one or more RISC-V processors. Spike is named after the golden spike used to celebrate the completion of the US transcontinental railway.

riscv-isa-manual - RISC-V Instruction Set Manual

  •    TeX

This repository contains the LaTeX source for the draft RISC-V Instruction Set Manual. At the time of this writing, none of these specifications have been formally adopted by the RISC-V Foundation. This work is licensed under a Creative Commons Attribution 4.0 International License. See the LICENSE file for details.

rocket-chip - Rocket Chip Generator

  •    Scala

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VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

  •    Assembly

For commercial support, please contact spinalhdl@gmail.com. The following numbers were obtained by synthesizing the CPU as toplevel without any specific synthesis options to save area or to get better maximal frequency (neutral). The clock constraint is set to an unattainable value, which tends to increase the design area. The dhrystone benchmark was compiled with the -O3 -fno-inline option. All the cached configurations have some cache trashing during the dhrystone benchmark except the VexRiscv full max perf one. This of course reduces the performance. It is possible to produce dhrystone binaries which fit inside a 4KB I$ and 4KB D$ (I already had this case once) but currently it isn't the case. The CPU configurations used below can be found in the src/scala/vexriscv/demo directory.

riscv-tools - RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)

  •    Shell

Note for OS X: We recommend using Homebrew to install the dependencies (libusb dtc gawk gnu-sed gmp mpfr libmpc isl wget automake md5sha1sum) or even to install the tools directly. This repo will build with Apple's command-line developer tools (clang) in addition to gcc.

pulpino - An open-source microcontroller system based on RISC-V

  •    C

PULPino is an open-source single-core microcontroller system, based on 32-bit RISC-V cores developed at ETH Zurich. PULPino is configurable to use either the RISCY or the zero-riscy core. RISCY is an in-order, single-issue core with 4 pipeline stages and it has an IPC close to 1, full support for the base integer instruction set (RV32I), compressed instructions (RV32C) and multiplication instruction set extension (RV32M). It can be configured to have single-precision floating-point instruction set extension (RV32F). It implements several ISA extensions such as: hardware loops, post-incrementing load and store instructions, bit-manipulation instructions, MAC operations, support fixed-point operations, packed-SIMD instructions and the dot product. It has been designed to increase the energy efficiency of in ultra-low-power signal processing applications. RISCY implementes a subset of the 1.9 privileged specification. Further informations can be found in http://ieeexplore.ieee.org/abstract/document/7864441/.

riscv-linux - RISC-V Linux Port

  •    C

RISC-V Linux Port

riscv-qemu - QEMU with RISC-V (RV64G, RV32G) Emulation Support

  •    C

QEMU with RISC-V (RV64G, RV32G) Emulation Support

e200_opensource - The Ultra-Low Power RISC Core

  •    Verilog

This repository hosts the project for open-source hummingbird E200 RISC processor Core. The Hummingbird E200 core is a two-stages pipeline based ultra-low power/area implementation, which has both performance and areas benchmark better than ARM Cortex-M0+ core, makes the Hummingbird E200 as a perfect replacement for legacy 8051 core or ARM Cortex-M cores in the IoT or other ultra-low power applications.

fusesoc - FuseSoC is a package manager and a set of build tools for FPGA/ASIC development

  •    Python

FuseSoC is an award-winning package manager and a set of build tools for HDL (Hardware Description Language) code. Its main purpose is to increase reuse of IP (Intellectual Property) cores and be an aid for creating, building and simulating SoC solutions.

vunit - VUnit is a unit testing framework for VHDL/SystemVerilog

  •    VHDL

VUnit is an open source unit testing framework for VHDL/SystemVerilog released under the terms of Mozilla Public License, v. 2.0. It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn't replace but rather complements traditional testing methodologies by supporting a "test early and often" approach through automation. Contributing in the form of code, feedback, ideas or bug reports are welcome. Read our contribution guide to get started.

cgminer - ASIC / FPGA / GPU miner in c for bitcoin and litecoin

  •    bitcoin

This is a multi-threaded multi-pool GPU, FPGA and ASIC miner with ATI GPU monitoring, (over)clocking and fanspeed support for bitcoin and derivative coins. Do not use on multiple block chains at the same time!

ckb - CKB is a public/permissionless blockchain, the layer 1 of Nervos network.

  •    Rust

CKB is the layer 1 of Nervos Network, a public/permissionless blockchain. CKB uses Proof of Work and improved Nakamoto concensus to achieve maximized performance on average hardware and internet condition, without sacrificing decentralization and security which are the core value of blockchain. CKB supports scripting in any programming language with its own CKB-VM, a virtual machine fully compatible with RISC-V ISA. CKB is a General Verification Network, its programming model focuses on state verification, leaves state generation to layer 2 applications/protocols.

picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU

  •    Verilog

PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller. Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website. The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. See the build instructions below for details.

Free tools and cores for FPGAs

  •    C

Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.

swerv_eh1 - A directory of Western Digital’s RISC-V SweRV Cores

  •    SystemVerilog

By contributing to this project, you agree that your contribution is governed by Apache-2.0. Files under the tools directory may be available under a different license. Please review individual file for details. This will update the default snapshot in $RV_ROOT/configs/snapshots/default/ with parameters for a 64K DCCM.

oh - Silicon proven Verilog library for IC and FPGA designers

  •    Verilog

OH! is an open-source library of hardware building blocks based on silicon proven design practices at 0.35um to 28nm. The library is being used by Adapteva in designing its next generation ASIC. The library is written in standard Verilog (2005) and contains over 25,000 lines of Verilog code, over 150 separate modules. Examples of functionality include: FIFOs, SPI (master/slave), GPIO, high speed links, memories, clock circuits, synchronization primitives,interrupt controller, DMA.

eclipse-plugins - The GNU MCU Eclipse plug-ins for ARM & RISC-V C/C++ developers

  •    C

These are the Eclipse projects used to build the GNU MCU Eclipse plug-ins. For new installs, the preferred method is via GNU MCU Eclipse IDE for C/C++ Developers , which packs the official Eclipse IDE for C/C++ Developers release with all GNU MCU Eclipse plug-ins already installed.