ariane - Ariane is a 6-stage RISC-V CPU

  •        86

Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M and C extensions as specified in Volume I: User-Level ISA V 2.1 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore it is compliant to the draft external debug spec 0.13. It has configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer and branch history table). The primary design goal was on reducing critical path length.



Related Projects

vunit - VUnit is a unit testing framework for VHDL/SystemVerilog

  •    VHDL

VUnit is an open source unit testing framework for VHDL/SystemVerilog released under the terms of Mozilla Public License, v. 2.0. It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn't replace but rather complements traditional testing methodologies by supporting a "test early and often" approach through automation. Contributing in the form of code, feedback, ideas or bug reports are welcome. Read our contribution guide to get started.

riscv-boom - Berkeley Out-of-Order Machine

  •    Scala

This is the source repository for the RV64G RISC-V superscalar Berkeley Out-of-Order Machine (BOOM), written in the Chisel hardware construction language. BOOM is a synthesizable core that targets ASIC processes. It can run on an FPGA (50 MHz on a zc706), but optimizing it to be an FPGA soft-core is a non-goal. For documentation on BOOM visit (

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

  •    Assembly

For commercial support, please contact The following numbers were obtained by synthesizing the CPU as toplevel without any specific synthesis options to save area or to get better maximal frequency (neutral). The clock constraint is set to an unattainable value, which tends to increase the design area. The dhrystone benchmark was compiled with the -O3 -fno-inline option. All the cached configurations have some cache trashing during the dhrystone benchmark except the VexRiscv full max perf one. This of course reduces the performance. It is possible to produce dhrystone binaries which fit inside a 4KB I$ and 4KB D$ (I already had this case once) but currently it isn't the case. The CPU configurations used below can be found in the src/scala/vexriscv/demo directory.

fusesoc - FuseSoC is a package manager and a set of build tools for FPGA/ASIC development

  •    Python

FuseSoC is an award-winning package manager and a set of build tools for HDL (Hardware Description Language) code. Its main purpose is to increase reuse of IP (Intellectual Property) cores and be an aid for creating, building and simulating SoC solutions.

hdl - HDL libraries and projects

  •    Verilog

Analog Devices Inc. HDL libraries and projects. This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.

cgminer - ASIC / FPGA / GPU miner in c for bitcoin and litecoin

  •    bitcoin

This is a multi-threaded multi-pool GPU, FPGA and ASIC miner with ATI GPU monitoring, (over)clocking and fanspeed support for bitcoin and derivative coins. Do not use on multiple block chains at the same time!

lowrisc-chip - The root repo for lowRISC project and FPGA demos.

  •    SystemVerilog

The root git repo for lowRISC development and FPGA demos.

Rapid HDL


Rapid Hardware Definition Language (Rapid HDL) is an object oriented C# software library in to script/generate/build synthesizable Verilog for FPGA hardware and software co-design in Visual Studio. It also integrates and automates Xilinx or Mentor Graphics build tools.

Pulp - Software Repository Management

  •    Python

Pulp is a platform for managing repositories of content, such as software packages, and pushing that content out to large numbers of consumers. If you want to locally mirror all or part of a repository, host your own content in a new repository, manage content from multiple sources in one place, and push content you choose out to large numbers of clients in one simple operation. Pulp has a well-documented REST API and command line interface for management.


  •    Java

HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.

freedom - Source files for SiFive's Freedom platforms

  •    Scala

This repository contains the RTL created by SiFive for its Freedom E300 and U500 platforms. The Freedom E310 Arty FPGA Dev Kit implements the Freedom E300 Platform and is designed to be mapped onto an Arty FPGA Evaluation Kit. The Freedom U500 VC707 FPGA Dev Kit implements the Freedom U500 Platform and is designed to be mapped onto a VC707 FPGA Evaluation Kit. Both systems boot autonomously and can be controlled via an external debugger. Please read the section corresponding to the kit you are interested in for instructions on how to use this repo.

bfgminer - Bitcoin miner

  •    C

Modular ASIC/FPGA miner written in C, featuring overclocking, monitoring, fan speed control and remote interface capabilities.

oh - Silicon proven Verilog library for IC and FPGA designers

  •    Verilog

OH! is an open-source library of hardware building blocks based on silicon proven design practices at 0.35um to 28nm. The library is being used by Adapteva in designing its next generation ASIC. The library is written in standard Verilog (2005) and contains over 25,000 lines of Verilog code, over 150 separate modules. Examples of functionality include: FIFOs, SPI (master/slave), GPIO, high speed links, memories, clock circuits, synchronization primitives,interrupt controller, DMA.

cpu_features - A cross platform C99 library to get cpu features at runtime.

  •    C

A cross-platform C library to retrieve CPU features (such as available instructions) at runtime. If you wish, you can read all the features at once into a global variable, and then query for the specific features you care about. Below, we store all the ARM features and then check whether AES and NEON are supported.


  •    C

OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.

ONIE - Open Network Install Environment

  •    C

The Open Network Install Environment (ONIE) is an open source initiative that defines an open "install environment" for modern networking hardware. ONIE enables an open networking hardware ecosystem where end users have a choice among different network operating systems.



vcores is a platform emulator, emulating a cpu and its platform. Vcores differs from other emulators as it allows a cpu to be emulated with several cores, even when the cpu hardware only currently has single core ALU's.

pidusage - Cross-platform process cpu % and memory usage of a PID

  •    Javascript

Cross-platform process cpu % and memory usage of a PID. Ideas from but with no C-bindings.

rocket-chip - Rocket Chip Generator

  •    Scala

This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core. For more information on Rocket Chip, please consult our technical report. To build the rocket-chip repository, you must point the RISCV environment variable to your riscv-tools installation directory.

Verilog HDL OOP Simulation/IDE


Simulate Verilog HDL without compiling to RTL. Instead, instantiate objects that run the HDL directly. A debugger that can then set breakpoints. single step, set watches, etc. then becomes feasable. C# makes it easy to parse HDL and simulate. Prototype code and two simpl...