RISCV_CPU - A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

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This project is a FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL, a course project of Computer Architecture(MS108), ACM honor class @ SJTU. This project is a simple five stage pipelined cpu for risc-v (rv32i) written in verilog HDL.

https://github.com/Michaelvll/RISCV_CPU

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