openofdm - Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

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See full documentation at http://openofdm.readthedocs.io. In a nutshell, the top level dot11 Verilog module takes 32-bit I/Q samples (16-bit each) as input, and output decoded bytes in 802.11 packet. The sampling rate is 20 MSPS and the clock rate is 100 MHz. This means this module expects one pair of I/Q sample every 5 clock ticks.

http://openofdm.rtfd.io
https://github.com/jhshi/openofdm

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