riscy - Riscy Processors - Open-Sourced RISC-V Processors

  •        6

This repository contains a collection of open-sourced RISC-V processors written in Bluespec System Verilog (BSV). These processors can be built with a variety of backends to use the processors in different simulation frameworks or FPGA. Currently the supported backends are Connectal and Verilator. Connectal is a generic framework that supports a variety of FPGAs and simulation targets.

https://github.com/csail-csg/riscy

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