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VLSI UtilsThe vlsi-utils project contains several utilities designed to ease the development of ASIC and FPGA designs. These utilities are written in Python, and have been tested under Red Hat Enterprise Linux and Ubuntu Linux. ComponentsRegenerate - A graphical interface that captures information about the registers in a design. It can generate synthesizable RTL code, documentation in OpenOffice format, and header files for C, Assembler, and Verilog. simon - A script that can be used to assist