PyHVL

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PyHVL is a hardware verification language that integrates Python with Verilog.

http://pyhvl.sourceforge.net

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Related Projects

Distributedpyhvl - attach python to verilog simulators


this project is to explore using python as a the glue to tie multiple instances of the verilog simulation language together, in a multiprocessor configuration. It relies heavily on the pyhvl project at pyhvl.sourceforge.net